Download Comp Arch Torrent

Torrent Contents Size: 3.38 GB

Comp Arch

Video Lecture

L1 - Instrction Set Architecture

1 - 1 - L1S1 Course Overview (434) (1).mp4	MP4	18.59 MB
1 - 1 - L1S1 Course Overview (434).mp4	MP4	18.59 MB
1 - 2 - L1S2 Motivation (1640).mp4	MP4	43.27 MB
1 - 3 - L1S3 Course Content (910).mp4	MP4	25.75 MB
1 - 4 - L1S4 Architecture and Microarchitecture (2337).mp4	MP4	52.83 MB
1 - 5 - L1S5 Machine Models (1602).mp4	MP4	32.83 MB
1 - 6 - L1S6 ISA Characteristics (2547).mp4	MP4	58.02 MB
1 - 7 - L1S7 Recap (0117).mp4	MP4	1.92 MB

L10-Branch Prediction

10 - 1 - L10S1 Branch Cost Motivation (637).mp4	MP4	12.05 MB
10 - 2 - L10S2 Branch Prediction Introduction (518).mp4	MP4	9.36 MB
10 - 3 - L10S3 Static Outcome Prediction (1605).mp4	MP4	29.34 MB
10 - 4 - L10S4 Dynamic Outcome Prediction (2912).mp4	MP4	54.05 MB
10 - 5 - L10S5 Target Address Prediction (1845).mp4	MP4	35.72 MB

L11-Advanced Caches 1

11 - 1 - L11S1 Basic Cache Optimizations (1608).mp4	MP4	34.49 MB
11 - 2 - L11S2 Cache Pipelining (1416).mp4	MP4	28.37 MB
11 - 3 - L11S3 Write Buffers (952).mp4	MP4	21.52 MB
11 - 4 - L11S4 Multilevel Caches (1737).mp4	MP4	33.01 MB
11 - 5 - L11S5 Victim Caches (604).mp4	MP4	13.25 MB
11 - 6 - L11S6 Prefetching (1234).mp4	MP4	25.48 MB

L12-Advanced Caches 2

12 - 1 - L12S1 Multiporting and Banking (2008).mp4	MP4	48.59 MB
12 - 2 - L12S2 Software Memory Optimizations (1653).mp4	MP4	70.87 MB
12 - 3 - L12S3 Non-blocking Caches (1929).mp4	MP4	42.11 MB
12 - 4 - L12S4 Critical Word First and Early Restart (306).mp4	MP4	7.03 MB

L13-Memory Protection

13 - 1 - L13S1 Memory Management Introduction (1304).mp4	MP4	32.06 MB
13 - 2 - L13S2 Base and Bound Registers (1144).mp4	MP4	26.02 MB
13 - 3 - L13S3 Page Based Memory Systems (2704).mp4	MP4	61.9 MB
13 - 4 - L13S4 Translation and Protection (1437).mp4	MP4	33.57 MB
13 - 5 - L13S5 TLB Processing (1200).mp4	MP4	26.04 MB

L14-Vector Processors & GPU

14 - 1 - L14S1 Address Translation Review (936).mp4	MP4	22.7 MB
14 - 2 - L14S2 Cache and Memory Protection Interaction (2218).mp4	MP4	54.93 MB
14 - 3 - L14S3 Vector Processor Introduction (1804).mp4	MP4	44.55 MB
14 - 4 - L14S4 Vector Parallelism (644).mp4	MP4	13.84 MB
14 - 5 - L14S5 Vector Hardware Optimizations (1852).mp4	MP4	41.76 MB
14 - 6 - L14S6 Vector Software and Compiler Optimizations (554).mp4	MP4	11.84 MB

L15- Multithreading

15 - 1 - L15S1 Reduction Scatter_Gather and the Cray 1 (920).mp4	MP4	23.46 MB
15 - 2 - L15S2 SIMD (658).mp4	MP4	15.43 MB
15 - 3 - L15S3 GPUs (2002).mp4	MP4	45.16 MB
15 - 4 - L15S4 Multithreading Motivation (733).mp4	MP4	16.19 MB
15 - 5 - L15S5 Course-Grain Multithreading (2616).mp4	MP4	59.85 MB
15 - 6 - L15S6 Simultaneous Multithreading (1253).mp4	MP4	30.39 MB

L16- Parallel Programming 1

16 - 1 - L16S1 SMT Implementation (1719).mp4	MP4	32.98 MB
16 - 2 - L16S2 Introduction to Parallelism (1759).mp4	MP4	35.33 MB
16 - 3 - L16S3 Sequential Consistency (2100).mp4	MP4	40.5 MB
16 - 4 - L16S4 Introduction to Locks (0339).mp4	MP4	7.35 MB

L17- Parallel Programming 2

17 - 1 - L17S1 Sequential Consistency Review (348).mp4	MP4	8.52 MB
17 - 2 - L17S2 Locks and Semaphores (1001).mp4	MP4	18.9 MB
17 - 3 - L17S3 Atomic Operations (2711).mp4	MP4	51.27 MB
17 - 4 - L17S4 Memory Fences (1111).mp4	MP4	22.67 MB
17 - 5 - L17S5 Dekkers Algorithm (1413).mp4	MP4	28.64 MB

L18- Small Multi Processors

18 - 1 - L18S1 Locking Review (156).mp4	MP4	4.27 MB
18 - 2 - L18S2 Bus Implementation (1012).mp4	MP4	18.46 MB
18 - 3 - L18S3 Cache Coherence (1225).mp4	MP4	20.96 MB
18 - 4 - L18S4 Bus-Based Multiprocessors (1209).mp4	MP4	23.76 MB
18 - 5 - L18S5 Cache Coherence Protocols (3322).mp4	MP4	64.06 MB

L19- Multiprocessor Interconnect 1

19 - 1 - L19S1 More Cache Coherence Protocols (2116).mp4	MP4	41.83 MB
19 - 2 - L19S2 Introduction to Interconnection Networks (829).mp4	MP4	15.04 MB
19 - 3 - L19S3 Message Passing (2659).mp4	MP4	48.63 MB
19 - 4 - L19S4 Interconnect Design (1506).mp4	MP4	29.01 MB

L2 - Pipelining Review

2 - 1 - L2S1 Microcoded Microarchitecture (1408).mp4	MP4	37.76 MB
2 - 2 - L2S2 Pipeline Basics (3051).mp4	MP4	64.69 MB
2 - 3 - L2S3 Structural Hazard (1013).mp4	MP4	23.16 MB
2 - 4 - L2S4 Data Hazards (4633).mp4	MP4	92.93 MB

L20- Multiprocessor Interconnect 2

20 - 1 - L20S1 Networking Review (756).mp4	MP4	19.02 MB
20 - 2 - L20S2 Topology (1853).mp4	MP4	39.92 MB
20 - 3 - L20S3 Topology Parameters (1425).mp4	MP4	33.79 MB
20 - 4 - L20S4 Network Performance (1535).mp4	MP4	31.75 MB
20 - 5 - L20S5 Routing and Flow Control (2027).mp4	MP4	48.01 MB

L21- Large Multiprocessors

21 - 1 - L21S1 Credit Based Flow Control (723).mp4	MP4	14.15 MB
21 - 2 - L21S2 Deadlock (1009).mp4	MP4	18.85 MB
21 - 3 - L21S3 False Sharing (929).mp4	MP4	14.88 MB
21 - 4 - L21S4 Introduction to Directory Coherence (1255).mp4	MP4	22.5 MB
21 - 5 - L21S5 Implementation (2902).mp4	MP4	57.06 MB
21 - 6 - L21S6 Scalability of Directory Coherence (1331).mp4	MP4	23.86 MB

L3 - Cache Review

3 - 1 - L3S1 Control Hazards Jumps (1556).mp4	MP4	26.94 MB
3 - 2 - L3S2 Control Hazards Branch (2402).mp4	MP4	47.51 MB
3 - 3 - L3S3 Control Hazards Others(751).mp4	MP4	15.59 MB
3 - 4 - L3S4 Memory Technologies (2247).mp4	MP4	50.5 MB
3 - 5 - L3S5 Motivation for Caches (2225).mp4	MP4	44.03 MB

L4 - Superscalar 1

4 - 1 - L4S1 Classifying Caches (2807).mp4	MP4	56.88 MB
4 - 2 - L4S2 Cache Performance (1711).mp4	MP4	31.28 MB
4 - 3 - L4S3 Superscalar 1 (642).mp4	MP4	13.47 MB
4 - 4 - L4S4 Basic Two-way In-order Superscalar (456).mp4	MP4	9.48 MB
4 - 5 - L4S5 Fetch Logic and Alignment (1101).mp4	MP4	19.12 MB

L5 - Superscalar 2 & Exceptions

5 - 1 - L5S1 Baseline Superscalar and Alignment (416).mp4	MP4	8.49 MB
5 - 2 - L5S2 Interrupts and Bypassing (1213).mp4	MP4	23.66 MB
5 - 3 - L5S3 Interrupts and Exceptions (2925).mp4	MP4	57.23 MB
5 - 4 - L5S4 Introduction to Out-of-Order Processors (3053).mp4	MP4	61.92 MB

L6 - Superscalar 3

6 - 1 - L6S1 Review of Out-of-Order Processors (326).mp4	MP4	6.86 MB
6 - 2 - L6S2 I2O2 Processors (1958).mp4	MP4	38.79 MB
6 - 3 - L6S3 I2O1 Processors (2844).mp4	MP4	54.87 MB
6 - 4 - L6S4 IO3 Processors (1623).mp4	MP4	32.01 MB
6 - 5 - L6S5 IO2I Processors (431).mp4	MP4	8.07 MB

L7 - Superscalar 4

7 - 1 - L7S1 Speculation and Branch (1437).mp4	MP4	29.08 MB
7 - 2 - L7S2 Register Renaming Introduction (1108).mp4	MP4	22.14 MB
7 - 3 - L7S3 Register Renaming with Pointers to IQ and ROB (2454).mp4	MP4	50.5 MB
7 - 4 - L7S4 Register Renaming with Values in IQ and ROB (1214).mp4	MP4	24.47 MB
7 - 5 - L7S5 Memory Disambiguation (949).mp4	MP4	18.44 MB

L8 - VLIW 1

8 - 1 - L8S1 Limits of Out-of-Order Design Complexity (1313).mp4	MP4	25.64 MB
8 - 2 - L8S2 Introduction to VLIW (2157).mp4	MP4	42.25 MB
8 - 3 - L8S3 VLIW Compiler Optimizations (2120).mp4	MP4	40.04 MB
8 - 4 - L8S4 Classic VLIW Challenges (818).mp4	MP4	15.54 MB
8 - 5 - L8S5 Introduction to Predication (951).mp4	MP4	19.29 MB

L9 - VLIW 2

9 - 1 - L9S1 Scheduling Model Review (558).mp4	MP4	20.03 MB
9 - 2 - L9S2 Review of Predication (3048).mp4	MP4	73.24 MB
9 - 3 - L9S3 Predication Implementation (1006).mp4	MP4	23.85 MB
9 - 4 - L9S4 Speculation Execution (2602).mp4	MP4	49.14 MB
9 - 5 - L9S5 Dynamic Events and Clustered VLIWs (1042).mp4	MP4	23.22 MB
9 - 6 - L9S6 Case Study IA-64_Itanium (2110).mp4	MP4	49.11 MB

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Comp Arch

Torrent Contents Size: 3.38 GB

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