Download Learning Verilog for FPGA Development - LinkedIn Learning Torrent

Learning Verilog for FPGA Development - LinkedIn Learning

1. Hardware Description

1. Hardware description languages.mp4	MP4	6.61 MB
2. Digital systems.mp4	MP4	3.99 MB
3. Levels of abstraction.mp4	MP4	6.34 MB
4. Gate level.mp4	MP4	4.95 MB
5. Register-transfer level.mp4	MP4	6.9 MB

2. Basic Verilog Syntax

1. Verilog modules.mp4	MP4	6.74 MB
10. Boolean algebra expressions.mp4	MP4	1.73 MB
11. Continuous assignments.mp4	MP4	4.78 MB
12. Blocking assignments.mp4	MP4	7.38 MB
13. Nonblocking assignments.mp4	MP4	8.09 MB
14. Challenge From schematic to code.mp4	MP4	4.92 MB
15. Solution From schematic to code.mp4	MP4	10.41 MB
2. Instantiating modules.mp4	MP4	10.31 MB
3. Gates and primitives.mp4	MP4	4.64 MB
4. Registers and wires.mp4	MP4	2.96 MB
5. Range specification.mp4	MP4	8.47 MB
6. Numbers and constants.mp4	MP4	8.86 MB
7. Always blocks.mp4	MP4	1.78 MB
8. The if-else statement.mp4	MP4	3.96 MB
9. Case statements.mp4	MP4	4.62 MB

3. Simulation

4. Combinational Systems

1. Arithmetic and logic operators.mp4	MP4	5.86 MB
2. Challenge Make a 4-bit arithmetic logic unit (ALU).mp4	MP4	4.02 MB
3. Solution Make a 4-bit arithmetic logic unit (ALU).mp4	MP4	5.71 MB
4. Getting your ALU on a field-programmable gate array (FPGA).mp4	MP4	11.79 MB
5. A functional demo of the ALU.mp4	MP4	33.33 MB

5. Sequential Systems

1. Flip-flops.mp4	MP4	5.9 MB
2. Edge sensitivity.mp4	MP4	4.82 MB
3. A shift register example.mp4	MP4	8.6 MB
4. Challenge Make a clock divider.mp4	MP4	4.25 MB
5. Solution Make a clock divider.mp4	MP4	6.85 MB
6. Getting your clock divider on an FPGA.mp4	MP4	8.24 MB
7. A functional demo of the clock divider.mp4	MP4	18.2 MB

Conclusion

1. Next steps.mp4

MP4

3.09 MB

Introduction

1. Verilog Your key to digital design.mp4	MP4	6.56 MB
2. What you should know.mp4	MP4	1.31 MB
3. Setting up your environment.mp4	MP4	9.12 MB

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Learning Verilog for FPGA Development - LinkedIn Learning

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