|
|
1. Basic Concepts of Digital.mp4
|
MP4
|
19.3 MB
|
|
|
1. Basic Concepts of Digital.srt
|
SRT
|
1.8 KB
|
|
|
1. Digital Design Flow.mp4
|
MP4
|
28.2 MB
|
|
|
1. Digital Design Flow.srt
|
SRT
|
4.4 KB
|
|
|
1. Interface, Intity.mp4
|
MP4
|
8.2 MB
|
|
|
1. Interface, Intity.srt
|
SRT
|
2.1 KB
|
|
|
1. Uses of VHDL.mp4
|
MP4
|
18.6 MB
|
|
|
1. Uses of VHDL.srt
|
SRT
|
2.3 KB
|
|
|
10. ISE Software Area.mp4
|
MP4
|
26.8 MB
|
|
|
10. ISE Software Area.srt
|
SRT
|
4.5 KB
|
|
|
10. SR Latch.mp4
|
MP4
|
13.1 MB
|
|
|
10. SR Latch.srt
|
SRT
|
2 KB
|
|
|
10. Simulation.mp4
|
MP4
|
28.2 MB
|
|
|
10. Simulation.srt
|
SRT
|
3.2 KB
|
|
|
11. Changing the names of the signals.mp4
|
MP4
|
130.4 MB
|
|
|
11. Changing the names of the signals.srt
|
SRT
|
12.6 KB
|
|
|
11. New Source Wizard.mp4
|
MP4
|
33.1 MB
|
|
|
11. New Source Wizard.srt
|
SRT
|
3.9 KB
|
|
|
11. SR Latch.mp4
|
MP4
|
22.6 MB
|
|
|
11. SR Latch.srt
|
SRT
|
4.2 KB
|
|
|
12. ISE Design properties.mp4
|
MP4
|
43.9 MB
|
|
|
12. ISE Design properties.srt
|
SRT
|
4.2 KB
|
|
|
12. Port mapping.mp4
|
MP4
|
24.9 MB
|
|
|
12. Port mapping.srt
|
SRT
|
2.4 KB
|
|
|
12. SR Latch.mp4
|
MP4
|
30.4 MB
|
|
|
12. SR Latch.srt
|
SRT
|
5 KB
|
|
|
13. Performing in the input.mp4
|
MP4
|
14.8 MB
|
|
|
13. Performing in the input.srt
|
SRT
|
1.6 KB
|
|
|
13. SR Latch.mp4
|
MP4
|
30 MB
|
|
|
13. SR Latch.srt
|
SRT
|
4.2 KB
|
|
|
13. Synthesize.mp4
|
MP4
|
44.3 MB
|
|
|
13. Synthesize.srt
|
SRT
|
4 KB
|
|
|
14. BCD code to Excess-3.mp4
|
MP4
|
58.3 MB
|
|
|
14. BCD code to Excess-3.srt
|
SRT
|
819.2 B
|
|
|
14. ISE Schematic.mp4
|
MP4
|
46.5 MB
|
|
|
14. ISE Schematic.srt
|
SRT
|
4.4 KB
|
|
|
14. SR Latch.mp4
|
MP4
|
18.8 MB
|
|
|
14. SR Latch.srt
|
SRT
|
2.3 KB
|
|
|
15. ISE Signals.mp4
|
MP4
|
44.2 MB
|
|
|
15. ISE Signals.srt
|
SRT
|
3.6 KB
|
|
|
15. SR Latch.mp4
|
MP4
|
8.5 MB
|
|
|
15. SR Latch.srt
|
SRT
|
1.1 KB
|
|
|
15. Simulation Example.mp4
|
MP4
|
11.2 MB
|
|
|
15. Simulation Example.srt
|
SRT
|
921.6 B
|
|
|
16. Demultiplexter.mp4
|
MP4
|
96.7 MB
|
|
|
16. Demultiplexter.srt
|
SRT
|
7.1 KB
|
|
|
16. ISE warnings.mp4
|
MP4
|
54.6 MB
|
|
|
16. ISE warnings.srt
|
SRT
|
4.8 KB
|
|
|
16. SR Latch.mp4
|
MP4
|
22.5 MB
|
|
|
16. SR Latch.srt
|
SRT
|
4.2 KB
|
|
|
17. D latch.mp4
|
MP4
|
34.2 MB
|
|
|
17. D latch.srt
|
SRT
|
3.9 KB
|
|
|
17. SR Latch.mp4
|
MP4
|
8.3 MB
|
|
|
17. SR Latch.srt
|
SRT
|
1.1 KB
|
|
|
18. Seneric inside NTT.mp4
|
MP4
|
124.1 MB
|
|
|
18. Seneric inside NTT.srt
|
SRT
|
11.2 KB
|
|
|
18. Timing Diagram.mp4
|
MP4
|
24.4 MB
|
|
|
18. Timing Diagram.srt
|
SRT
|
4.9 KB
|
|
|
19. SR Latch Timing Diagram.mp4
|
MP4
|
11.6 MB
|
|
|
19. SR Latch Timing Diagram.srt
|
SRT
|
2.3 KB
|
|
|
19. Simulation Example.mp4
|
MP4
|
33.9 MB
|
|
|
19. Simulation Example.srt
|
SRT
|
3 KB
|
|
|
2. ASIC Digital Flow.mp4
|
MP4
|
33 MB
|
|
|
2. ASIC Digital Flow.srt
|
SRT
|
4.8 KB
|
|
|
2. Basic Concepts of Digital.mp4
|
MP4
|
42.9 MB
|
|
|
2. Basic Concepts of Digital.srt
|
SRT
|
4.8 KB
|
|
|
2. Before we start.mp4
|
MP4
|
15.9 MB
|
|
|
2. Before we start.srt
|
SRT
|
2.1 KB
|
|
|
2. Ports in VHDL.mp4
|
MP4
|
12.8 MB
|
|
|
2. Ports in VHDL.srt
|
SRT
|
3.3 KB
|
|
|
20. Propagation.mp4
|
MP4
|
30.2 MB
|
|
|
20. Propagation.srt
|
SRT
|
3.5 KB
|
|
|
20. SR Latch State Diagram.mp4
|
MP4
|
27.5 MB
|
|
|
20. SR Latch State Diagram.srt
|
SRT
|
6.2 KB
|
|
|
21. Generic Example.mp4
|
MP4
|
71.6 MB
|
|
|
21. Generic Example.srt
|
SRT
|
7.2 KB
|
|
|
21. SR Latch.mp4
|
MP4
|
21.6 MB
|
|
|
21. SR Latch.srt
|
SRT
|
6.2 KB
|
|
|
22. ISE Library Section.mp4
|
MP4
|
70.1 MB
|
|
|
22. ISE Library Section.srt
|
SRT
|
7 KB
|
|
|
22. SR Latch with Enable.mp4
|
MP4
|
17.4 MB
|
|
|
22. SR Latch with Enable.srt
|
SRT
|
3.7 KB
|
|
|
23. D Latch.mp4
|
MP4
|
24.6 MB
|
|
|
23. D Latch.srt
|
SRT
|
4.4 KB
|
|
|
23. Herarchial and External Naming.mp4
|
MP4
|
35.7 MB
|
|
|
23. Herarchial and External Naming.srt
|
SRT
|
4.3 KB
|
|
|
24. D Latch Timing Diagram.mp4
|
MP4
|
15.7 MB
|
|
|
24. D Latch Timing Diagram.srt
|
SRT
|
4.5 KB
|
|
|
24. Type conversions.mp4
|
MP4
|
29.8 MB
|
|
|
24. Type conversions.srt
|
SRT
|
4 KB
|
|
|
25. D Latch characteristic.mp4
|
MP4
|
20.5 MB
|
|
|
25. D Latch characteristic.srt
|
SRT
|
4.1 KB
|
|
|
25. Type Conversion Chart.mp4
|
MP4
|
23.1 MB
|
|
|
25. Type Conversion Chart.srt
|
SRT
|
2.6 KB
|
|
|
26. D Latch with transmission gate.mp4
|
MP4
|
9.8 MB
|
|
|
26. D Latch with transmission gate.srt
|
SRT
|
2.5 KB
|
|
|
26. Type Conversion in ISE.mp4
|
MP4
|
49.1 MB
|
|
|
26. Type Conversion in ISE.srt
|
SRT
|
3.5 KB
|
|
|
27. D Latch with transmission gate.mp4
|
MP4
|
21.9 MB
|
|
|
27. D Latch with transmission gate.srt
|
SRT
|
4.1 KB
|
|
|
27. Type Conversion Simulation.mp4
|
MP4
|
92.9 MB
|
|
|
27. Type Conversion Simulation.srt
|
SRT
|
9.4 KB
|
|
|
28. JK Latch.mp4
|
MP4
|
13.2 MB
|
|
|
28. JK Latch.srt
|
SRT
|
3.2 KB
|
|
|
29. JK Latch.mp4
|
MP4
|
20.3 MB
|
|
|
29. JK Latch.srt
|
SRT
|
6 KB
|
|
|
3. Basic Concepts of Digital.mp4
|
MP4
|
13.2 MB
|
|
|
3. Basic Concepts of Digital.srt
|
SRT
|
1.5 KB
|
|
|
3. Generic.mp4
|
MP4
|
12 MB
|
|
|
3. Generic.srt
|
SRT
|
3.2 KB
|
|
|
3. System Level Digital Flow.mp4
|
MP4
|
7 MB
|
|
|
3. System Level Digital Flow.srt
|
SRT
|
1.5 KB
|
|
|
3. Verilog vs VHDL.mp4
|
MP4
|
20 MB
|
|
|
3. Verilog vs VHDL.srt
|
SRT
|
2.8 KB
|
|
|
30. Flip Flops.mp4
|
MP4
|
18.7 MB
|
|
|
30. Flip Flops.srt
|
SRT
|
4.1 KB
|
|
|
31. Flip Flops.mp4
|
MP4
|
30.1 MB
|
|
|
31. Flip Flops.srt
|
SRT
|
5 KB
|
|
|
32. D Flip Flops.mp4
|
MP4
|
9.1 MB
|
|
|
32. D Flip Flops.srt
|
SRT
|
2.3 KB
|
|
|
33. D Flip Flops.mp4
|
MP4
|
28 MB
|
|
|
33. D Flip Flops.srt
|
SRT
|
4.8 KB
|
|
|
34. D Flip Flops.mp4
|
MP4
|
20.4 MB
|
|
|
34. D Flip Flops.srt
|
SRT
|
4 KB
|
|
|
35. D Flip Flops.mp4
|
MP4
|
17.3 MB
|
|
|
35. D Flip Flops.srt
|
SRT
|
2.8 KB
|
|
|
36. Latch vs Flip Flop.mp4
|
MP4
|
8.4 MB
|
|
|
36. Latch vs Flip Flop.srt
|
SRT
|
1.2 KB
|
|
|
37. Latch vs Flip Flop.mp4
|
MP4
|
22 MB
|
|
|
37. Latch vs Flip Flop.srt
|
SRT
|
2.8 KB
|
|
|
38. Latch vs Flip Flop.mp4
|
MP4
|
25.5 MB
|
|
|
38. Latch vs Flip Flop.srt
|
SRT
|
3.5 KB
|
|
|
39. Rising Edge D-FF.mp4
|
MP4
|
16.2 MB
|
|
|
39. Rising Edge D-FF.srt
|
SRT
|
4.4 KB
|
|
|
4. New Project Wizard.mp4
|
MP4
|
26.3 MB
|
|
|
4. New Project Wizard.srt
|
SRT
|
2.7 KB
|
|
|
4. Reprogammable Devices.mp4
|
MP4
|
21.3 MB
|
|
|
4. Reprogammable Devices.srt
|
SRT
|
4.8 KB
|
|
|
4. Sequential vs combinational.mp4
|
MP4
|
13.2 MB
|
|
|
4. Sequential vs combinational.srt
|
SRT
|
4.2 KB
|
|
|
4. VHDL.mp4
|
MP4
|
4.9 MB
|
|
|
4. VHDL.srt
|
SRT
|
1.9 KB
|
|
|
40. Rising Edge D-FF.mp4
|
MP4
|
21.1 MB
|
|
|
40. Rising Edge D-FF.srt
|
SRT
|
3.8 KB
|
|
|
41. Master Slave FF.mp4
|
MP4
|
23.9 MB
|
|
|
41. Master Slave FF.srt
|
SRT
|
4.4 KB
|
|
|
42. T Flip Flop.mp4
|
MP4
|
13.6 MB
|
|
|
42. T Flip Flop.srt
|
SRT
|
3.4 KB
|
|
|
43. Asynchronous Preset.mp4
|
MP4
|
13.5 MB
|
|
|
43. Asynchronous Preset.srt
|
SRT
|
3.3 KB
|
|
|
44. Synchronous Reset.mp4
|
MP4
|
25.8 MB
|
|
|
44. Synchronous Reset.srt
|
SRT
|
4.7 KB
|
|
|
45. Additional Inputs of Flip Flop.mp4
|
MP4
|
9.4 MB
|
|
|
45. Additional Inputs of Flip Flop.srt
|
SRT
|
2.7 KB
|
|
|
46. Setup time, Hold Time, Delay types.mp4
|
MP4
|
12.7 MB
|
|
|
46. Setup time, Hold Time, Delay types.srt
|
SRT
|
2.8 KB
|
|
|
47. Setup time, Hold Time, Delay types.mp4
|
MP4
|
37 MB
|
|
|
47. Setup time, Hold Time, Delay types.srt
|
SRT
|
4.5 KB
|
|
|
48. Timing Requirements.mp4
|
MP4
|
18.6 MB
|
|
|
48. Timing Requirements.srt
|
SRT
|
4.8 KB
|
|
|
49. Timing Requirements.mp4
|
MP4
|
9.2 MB
|
|
|
49. Timing Requirements.srt
|
SRT
|
1.6 KB
|
|
|
5. Common Components.mp4
|
MP4
|
16.6 MB
|
|
|
5. Common Components.srt
|
SRT
|
2.1 KB
|
|
|
5. Sequential vs combinational.mp4
|
MP4
|
9 MB
|
|
|
5. Sequential vs combinational.srt
|
SRT
|
2.3 KB
|
|
|
5. Synchronizing.mp4
|
MP4
|
34.9 MB
|
|
|
5. Synchronizing.srt
|
SRT
|
2.9 KB
|
|
|
50. Timing Requirements.mp4
|
MP4
|
35.8 MB
|
|
|
50. Timing Requirements.srt
|
SRT
|
5 KB
|
|
|
51. Timing Requirements.mp4
|
MP4
|
21.4 MB
|
|
|
51. Timing Requirements.srt
|
SRT
|
3.7 KB
|
|
|
52. Synchronous vs Asynchronous.mp4
|
MP4
|
48.5 MB
|
|
|
52. Synchronous vs Asynchronous.srt
|
SRT
|
6 KB
|
|
|
53. Clock Signals.mp4
|
MP4
|
9.1 MB
|
|
|
53. Clock Signals.srt
|
SRT
|
1.6 KB
|
|
|
54. Synchronous circuits.mp4
|
MP4
|
17.6 MB
|
|
|
54. Synchronous circuits.srt
|
SRT
|
4.2 KB
|
|
|
55. Sequential circuit analysis.mp4
|
MP4
|
6.2 MB
|
|
|
55. Sequential circuit analysis.srt
|
SRT
|
1.1 KB
|
|
|
56. Sequential circuit.mp4
|
MP4
|
14.2 MB
|
|
|
56. Sequential circuit.srt
|
SRT
|
2 KB
|
|
|
57. Sequential circuit.mp4
|
MP4
|
26.6 MB
|
|
|
57. Sequential circuit.srt
|
SRT
|
4.8 KB
|
|
|
58. Sequential circuit.mp4
|
MP4
|
17.7 MB
|
|
|
58. Sequential circuit.srt
|
SRT
|
2.5 KB
|
|
|
59. Sequential circuit.mp4
|
MP4
|
26 MB
|
|
|
59. Sequential circuit.srt
|
SRT
|
4.3 KB
|
|
|
6. Encoder.mp4
|
MP4
|
8.4 MB
|
|
|
6. Encoder.srt
|
SRT
|
1.5 KB
|
|
|
6. FIFO.mp4
|
MP4
|
21.1 MB
|
|
|
6. FIFO.srt
|
SRT
|
3.7 KB
|
|
|
6. Sequential logic idea.mp4
|
MP4
|
24.6 MB
|
|
|
6. Sequential logic idea.srt
|
SRT
|
3.9 KB
|
|
|
60. Sequential circuit.mp4
|
MP4
|
25.7 MB
|
|
|
60. Sequential circuit.srt
|
SRT
|
4.9 KB
|
|
|
61. State table.mp4
|
MP4
|
16.1 MB
|
|
|
61. State table.srt
|
SRT
|
2.5 KB
|
|
|
62. PLD Family.mp4
|
MP4
|
17 MB
|
|
|
62. PLD Family.srt
|
SRT
|
3.4 KB
|
|
|
63. Mask Programming Devices.mp4
|
MP4
|
8.2 MB
|
|
|
63. Mask Programming Devices.srt
|
SRT
|
2.2 KB
|
|
|
64. PLA.mp4
|
MP4
|
8.2 MB
|
|
|
64. PLA.srt
|
SRT
|
2.4 KB
|
|
|
65. GLA.mp4
|
MP4
|
13.2 MB
|
|
|
65. GLA.srt
|
SRT
|
1.8 KB
|
|
|
66. CPLD.mp4
|
MP4
|
13.2 MB
|
|
|
66. CPLD.srt
|
SRT
|
1.6 KB
|
|
|
67. CPLD IC.mp4
|
MP4
|
22 MB
|
|
|
67. CPLD IC.srt
|
SRT
|
2.5 KB
|
|
|
68. CPLD Architecture.mp4
|
MP4
|
10 MB
|
|
|
68. CPLD Architecture.srt
|
SRT
|
1.8 KB
|
|
|
69. FPGA.mp4
|
MP4
|
18.8 MB
|
|
|
69. FPGA.srt
|
SRT
|
3.4 KB
|
|
|
7. Designing the Gate Level.mp4
|
MP4
|
66.8 MB
|
|
|
7. Designing the Gate Level.srt
|
SRT
|
4.7 KB
|
|
|
7. Sequential logic idea.mp4
|
MP4
|
68.4 MB
|
|
|
7. Sequential logic idea.srt
|
SRT
|
11.8 KB
|
|
|
7. UART.mp4
|
MP4
|
20.2 MB
|
|
|
7. UART.srt
|
SRT
|
2.9 KB
|
|
|
70. FPGA Architecture.mp4
|
MP4
|
8.9 MB
|
|
|
70. FPGA Architecture.srt
|
SRT
|
2.2 KB
|
|
|
71. FPGA Architecture.mp4
|
MP4
|
23.7 MB
|
|
|
71. FPGA Architecture.srt
|
SRT
|
3.8 KB
|
|
|
72. FPGA Architecture.mp4
|
MP4
|
16.1 MB
|
|
|
72. FPGA Architecture.srt
|
SRT
|
1.5 KB
|
|
|
73. FPGA & CPLD Usage.mp4
|
MP4
|
35.7 MB
|
|
|
73. FPGA & CPLD Usage.srt
|
SRT
|
4 KB
|
|
|
74. FPGA, SystemC, Verilog.mp4
|
MP4
|
28.9 MB
|
|
|
74. FPGA, SystemC, Verilog.srt
|
SRT
|
4 KB
|
|
|
75. ISE Install.mp4
|
MP4
|
23.9 MB
|
|
|
75. ISE Install.srt
|
SRT
|
2.1 KB
|
|
|
8. FIFO operation.mp4
|
MP4
|
45.4 MB
|
|
|
8. FIFO operation.srt
|
SRT
|
3.5 KB
|
|
|
8. SR Latch.mp4
|
MP4
|
6.8 MB
|
|
|
8. SR Latch.srt
|
SRT
|
1.6 KB
|
|
|
8. Test Bench.mp4
|
MP4
|
11.5 MB
|
|
|
8. Test Bench.srt
|
SRT
|
2.7 KB
|
|
|
9. General Purpose processor.mp4
|
MP4
|
39.2 MB
|
|
|
9. General Purpose processor.srt
|
SRT
|
4 KB
|
|
|
9. SR Latch.mp4
|
MP4
|
17.5 MB
|
|
|
9. SR Latch.srt
|
SRT
|
2.5 KB
|
|
|
9. Test Bench Types.mp4
|
MP4
|
111.9 MB
|
|
|
9. Test Bench Types.srt
|
SRT
|
11.2 KB
|
|
|
Bonus Resources.txt
|
TXT
|
307.2 B
|
|
|
Get Bonus Downloads Here.url
|
URL
|
204.8 B
|
