Download Udemy - Mastering Xilinx DSP IP Cores - FIR, CIC, DDS, FFT Torrent

Torrent Contents Size: 1.9 GB

Udemy - Mastering Xilinx DSP IP Cores - FIR, CIC, DDS, FFT

▼ show more 35 files

1 -Introduction.mp4	MP4	41.9 MB
1 -Vivado Simulation FIR compiler v7.2.mp4	MP4	311.7 MB
1 -Zynq 7000 SoC development C application to interface with FIR compiler IP cores.mp4	MP4	341.5 MB
2 -Requirements and Workflow Automation.mp4	MP4	115.4 MB
2 -Vivado Simulation CIC compiler v4.0.mp4	MP4	138.4 MB
2 -Zynq 7000 SoC development C application to interface with CIC compiler IP cores.mp4	MP4	298.6 MB
3 -Vivado Simulation DDS compiler v6.0.mp4	MP4	122.5 MB
3 -Zynq 7000 SoC development C application to interface with DDS compiler IP cores.mp4	MP4	224.3 MB
4 -Vivado Simulation Fast Fourier Transform v9.1.mp4	MP4	114.8 MB
4 -Zynq 7000 SoC development C application to interface with FFT IP core.mp4	MP4	255.8 MB
BPF.coe	COE	204.8 B
Bonus Resources.txt	TXT	102.4 B
Get Bonus Downloads Here.url	URL	204.8 B
LPF_dec.coe	COE	204.8 B
LPF_int.coe	COE	204.8 B
README.md	MD	2.1 KB
cic_compiler.py	PY	3.5 KB
cic_compiler_tb.v	V	3.9 KB
cic_compiler_tb_behav.wcfg	WCFG	4 KB
cic_hw.tcl	TCL	1.8 KB
cic_main.c	C	6.7 KB
cic_sys.tcl	TCL	45.9 KB
clean.py	PY	1.8 KB
create_vitis.py	PY	1.7 KB
dds_axi_wrapper.v	V	2.2 KB
dds_compiler.py	PY	4.9 KB
dds_compiler_tb.v	V	5.6 KB
dds_compiler_tb_behav.wcfg	WCFG	20.6 KB
dds_hw.tcl	TCL	2 KB
dds_main.c	C	7.2 KB
dds_sys.tcl	TCL	45.7 KB
dsp_sim.tcl	TCL	13.3 KB
fir_compiler.py	PY	4.1 KB
fir_compiler_tb.v	V	7.8 KB
fir_compiler_tb_behav.wcfg	WCFG	11.9 KB
fir_hw.tcl	TCL	1.7 KB
fir_main.c	C	8.8 KB
fir_sys.tcl	TCL	47.2 KB
gui_launcher.py	PY	2 KB
hilbert_0.coe	COE	716.8 B
run_sim.py	PY	2.3 KB
run_vitis.py	PY	2.7 KB
run_vivado.py	PY	2.5 KB
tb_util.vh	VH	7.3 KB
xfft.py	PY	5.7 KB
xfft_hw.tcl	TCL	1.7 KB
xfft_main.c	C	9.3 KB
xfft_sys.tcl	TCL	41.1 KB
xfft_tb.v	V	5.7 KB
xfft_tb_behav.wcfg	WCFG	28.7 KB

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Udemy - Mastering Xilinx DSP IP Cores - FIR, CIC, DDS, FFT

Torrent Contents Size: 1.9 GB

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