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Verilog

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TORRENT NAME	SIZE	FILES	AGE	SEEDS	LEECHS	SOURCE
Udemy - RTL Finite State Machines in System Verilog Posted by freecoursewb in Other Posted in Other 6 382.6 MB 1 year ago freecoursewb	Size 382.6 MB	Files 37	Age 1 year ago	Seeds 6	Leechs 0	Source
UART on Xilinx FPGA - Verilog Design, Vitis Software, Hardware Posted by freecoursewb in Other Posted in Other 6 801.5 MB 4 months ago freecoursewb	Size 801.5 MB	Files 0	Age 4 months ago	Seeds 6	Leechs 2	Source
Udemy - Learn System Verilog for Verification Posted by freecoursewb in Other Posted in Other 4 1.3 GB 6 months ago freecoursewb	Size 1.3 GB	Files 22	Age 6 months ago	Seeds 4	Leechs 3	Source
Udemy - Verilog HDL Fundamentals for Digital Design and Verification Posted by freecoursewb in Other Posted in Other 3 3.4 GB 4 years ago freecoursewb	Size 3.4 GB	Files 1	Age 4 years ago	Seeds 3	Leechs 0	Source
[ DevCourseWeb ] Udemy - Verilog on Intel (Altera) FPGA Posted by freecoursewb in Other Posted in Other 3 2.9 GB 5 years ago freecoursewb	Size 2.9 GB	Files 1	Age 5 years ago	Seeds 3	Leechs 1	Source
Udemy - Simple Axi Bus Design Using Verilog Hdl Posted by freecoursewb in Other Posted in Other 2 595.2 MB 2 years ago freecoursewb	Size 595.2 MB	Files 27	Age 2 years ago	Seeds 2	Leechs 0	Source
Udemy - Digital Systems and Logic Design with verilog codes Posted by freecoursewb in Other Posted in Other 2 735.3 MB 4 years ago freecoursewb	Size 735.3 MB	Files 29	Age 4 years ago	Seeds 2	Leechs 1	Source
[ FreeCourseWeb ] Lynda - Learning Verilog for FPGA Development Posted by freecoursewb in Other Posted in Other 2 307.4 MB 6 years ago freecoursewb	Size 307.4 MB	Files 1	Age 6 years ago	Seeds 2	Leechs 0	Source
[ DevCourseWeb ] Udemy - Writing System Verilog Testbenches for Newbie Posted by freecoursewb in Other Posted in Other 1 1.1 GB 5 years ago freecoursewb	Size 1.1 GB	Files 1	Age 5 years ago	Seeds 1	Leechs 0	Source
Udemy - UART Design and Simulation using Verilog HDL programming Posted by freecoursewb in Other Posted in Other 1 1.3 GB 4 years ago freecoursewb	Size 1.3 GB	Files 34	Age 4 years ago	Seeds 1	Leechs 2	Source
[ CourseWikia ] Udemy - Verilog HDL Through Examples Posted by freecoursewb in Other Posted in Other 1 1.7 GB 5 years ago freecoursewb	Size 1.7 GB	Files 1	Age 5 years ago	Seeds 1	Leechs 0	Source
[ FreeCourseWeb ] Udemy - FPGA Embedded Design, Part 1 - Verilog Posted by freecoursewb in Other Posted in Other 1 394 MB 6 years ago freecoursewb	Size 394 MB	Files 1	Age 6 years ago	Seeds 1	Leechs 0	Source
Udemy - SystemVerilog Beginner: Write Your First Design &TB Modules Posted by tutsgalaxy in Other Posted in Other 1 448.2 MB 6 years ago tutsgalaxy	Size 448.2 MB	Files 4	Age 6 years ago	Seeds 1	Leechs 1	Source
Learn SystemVerilog Assertions and Coverage Coding in-depth Posted by groovymax123 in Other Posted in Other 1 745 MB 11 years ago groovymax123	Size 745 MB	Files 26	Age 11 years ago	Seeds 1	Leechs 0	Source
Udemy - SystemVerilog Functional Coverage for Newbie Posted by freecoursewb in Other Posted in Other 0 2.4 GB 4 years ago freecoursewb	Size 2.4 GB	Files 196	Age 4 years ago	Seeds 0	Leechs 0	Source
SystemVerilog Design Start Programming Your Own ICs in HDL Posted by skydiving666 in Other Posted in Other 0 540.1 MB 10 years ago skydiving666	Size 540.1 MB	Files 3	Age 10 years ago	Seeds 0	Leechs 2	Source
Udemy - Verilog HDL programming with practical approach Posted by freecoursewb in Other Posted in Other 0 2.8 GB 4 years ago freecoursewb	Size 2.8 GB	Files 201	Age 4 years ago	Seeds 0	Leechs 0	Source
[ FreeCourseWeb ] Udemy - Verilog Interview Preparation Guide Posted by freecoursewb in Other Posted in Other 0 218.52 MB 5 years ago freecoursewb	Size 218.52 MB	Files 1	Age 5 years ago	Seeds 0	Leechs 1	Source
[ FreeCourseWeb ] Udemy - VLSI Digital Design using Verilog and hardware- Handso... Posted in Other Posted in Other 0 8 GB 6 years ago	Size 8 GB	Files 1	Age 6 years ago	Seeds 0	Leechs 2	Source

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